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2.7 v to 5.5 v, <100 a, 14-bit nano dac? d/a in sc70 package prelim inary technical data AD5641 rev. pr c in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 6-lea d sc7 0 pa ckage power-down to <100 na @ 3 v single 14-bit d a c: b versio n: 4 l s b inl a versio n: 8 l s b inl microp ower op eration: max 100 a @ 5 v 2.7 v to 5.5 v p o wer supply guaranteed m o notonic by design power-on reset to 0 v with brownout detection 3 power-down functions low power serial interface wit h schmitt-triggered inputs on-chip output buffer ampli f i e r, rail-to-rai l o p eration sync interrupt facili ty applic ati o ns voltage le vel s e tting portable batter y -powered inst ruments digital gain and offset adjustment programmable voltage an d current sources programmable attenuators general description the AD5641, a m e m b er o f the na no d a c f a m i l y , i s a s i n g l e , 14-b i t, b u f f er e d , v o l t a g e o u t d a c t h a t o p era t es f r o m a sin g le 2.7 v t o 5.5 v su p p l y , co n s umin g <100 a a t 5 v . the p a r t co m e s in a tin y sc70 p a c k a g e . i t s o n -chi p p r e c isio n o u t p u t a m p l if ier allo ws ra il-t o-ra il o u t p u t swin g t o be ac hiev e d . th e AD5641 u t ilizes a v e rs a t ile 3 - wir e s e r i al in t e r f ac e tha t o p era t es a t clo c k r a t e s u p t o 30 mh z and is co m p a t i b le w i t h spi?, qs pi? , mi cro w i r e? , a nd ds p in ter f ace st anda r d s. t h e r e fer e nce fo r AD5641 is der i v e d f r o m t h e p o w e r s u p p l y in p u ts an d , t h er ef o r e , g i v e s t h e wi des t d y na mic o u t p ut ra n g e . th e p a r t inco r p o r a t es a p o we r - on re s e t c i rc u i t , w h i c h e n su re s t h a t t h e d a c output p o w e rs u p t o 0 v a nd r e ma i n s t h er e un t i l a vali d wr i t e t o t h e de vice t a k e s pla c e. the AD5641 con t a i n s a p o w e r - do wn f e a t ur e tha t r e d u ces c u r r en t co n s um p t io n t o <100 na a t 3 v , a nd p r o v ides s o f t wa r e - s e le c t a b le ou t p u t lo ads while in p o w e r - do wn mo de . th e p a r t is p u t in t o p o w e r - do wn m o de o v er t h e s e r i al in t e r f ace . th e lo w p o w e r co n s um pt io n o f t h e p a r t in n o r m a l o p era t io n ma k e s i t i d eall y s u i t e d t o po r t a b l e ba t t e r y- o p e r a t ed e q ui p m en t . th e co m b in a t ion o f sma l l p a cka g e and lo w p o w e r ma k e s t h is na no d a c devi ce i d eal f o r l e v e l -se t tin g r e q u i r em en t s s u ch a s ge ne r a t i ng bi a s or c o n t ro l vo lt a g e s i n sp a c e - c o nst r ai ne d a n d p o w e r- s e n s i t i v e ap p l i c at i o n s . func tio n a l block di agram powe r-on rese t da c regist er 14- bit da c input control logic powe r- down control l ogic ad 5641 v dd gnd ref(+) resist or network v out sync sclk din output buffe r 04611-a - 001 fi g u r e 1 . table 1. r e lated d e vices part num b er descr iption ad5 601 /a d56 1 1 / ad 562 1 2.7 v to 5.5 v, <1 00 a, 8- /10 - /1 2- bit, nano dac? d/a, spi in terface, sc70 pa cka g e the AD5641 is desig n e d wi t h new tec h n o log y a nd com e s in a s p ace-s a vin g sc70 p a c k a g e . product highlights 1. a v a i la b l e in a sp ace-s a vi n g 6-le ad sc70 p a ck a g e. 2. l o w p o w e r , sin g le-s u p pl y o p er a t io n. th e ad564 1 o p era t es f r o m a sin g le 2. 7 v t o 5.5 v s u p p l y a n d typ i cal l y co n s um es 0.2 mw a t 3 v and 0.5 mw a t 5 v , makin g i t ide a l f o r b a t t e r y - p o w e r e d ap p l i c at i o n s . 3. t h e on - c h i p output bu f f e r am p l i f i e r a l l o w s t h e output of th e d a c t o sw in g ra il- t o- ra il wi th a t y p i cal s l e w ra t e o f 0.5 v/s. 4. refer e nce der i ve d f r o m t h e p o w e r su p p ly . 5. h i g h sp e e d s e r i a l in t e r f ace w i t h clo c k sp e e ds up t o 30 mh z. 6. design e d f o r v e r y l o w p o w e r co n s um p t io n . the in t e r f ace p o w e rs u p o n l y d u r i n g a wr i t e c y c l e . 7. p o w e r - do w n c a p a b i li ty . w h en p o w e r e d do w n , t h e d a c typ i cal l y co ns um es <100 na a t 3 v . 8. p o w e r - o n r e s e t wi t h b r o w no u t dete c t ion.
AD5641 preliminary technical data rev. prc | page 2 of 20 table of contents specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................ 6 te r m i no l o g y ...................................................................................... 7 typical performance characteristics ............................................. 8 general description ....................................................................... 12 d/a section ................................................................................. 12 resistor string ............................................................................. 12 output amplifier ........................................................................ 12 serial interface ............................................................................ 12 input shift register .................................................................... 12 sync interrupt .......................................................................... 13 power-on reset .......................................................................... 13 power-down modes .................................................................. 13 microprocessor interfacing ....................................................... 13 applications ..................................................................................... 15 choosing a reference as power supply for AD5641 ............. 15 bipolar operation using the AD5641 ..................................... 15 using AD5641 with an opto-isolated interface ..................... 16 power supply bypassing and grounding ................................ 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history revision prc: preliminary version
preliminary technical data AD5641 rev. prc | page 3 of 20 specifications v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; all specifications t min to t max , unless otherwise noted. table 2. b version 1 parameter min typ max unit test conditions/comments static performance resolution 14 bits relative accuracy 2 4 lsb b grade 8 lsb a grade differential nonlinearity 2 1 lsb guaranteed monotonic by design zero code error 0.2 mv a ll 0s loaded to dac register offset error 0.125 % of fsr full-scale error 0.01 lsb all 1s loaded to dac register gain error 0.04 % of fsr zero code error drift 5.0 v/c gain temperature coefficient 2.0 ppm of fsr/c output characteristics 3 output voltage range 0 v dd v output voltage settling time 8 18 s code ? to ? slew rate 0.5 v/s capacitive load stability 470 pf r l = 1000 pf rl = 2 k? output noise spectral density 120 nv/hz dac code = tbd, 10 khz noise tbd dac code = tbd, 0.1 hz to 10 hz bandwidth digital-to-analog glitch impulse 10 nv-s 1 lsb change around major carry digital feedthrough 0.5 nv-s dc output impedance 1 short-circuit current 20 ma v dd = 3 v/5 v logic inputs input current 1 a v inl , input low voltage 0.8 v v dd = 5 v 0.6 v v dd = 2.7 v v inh , input high voltage 1.8 v v dd = 5 v 1.4 v v dd = 2.7 v pin capacitance 3 pf power requirements v dd 2.7 5.5 v all digital inputs at 0 or v dd i dd (normal mode) dac active and excluding load current v dd = 4.5 v to 5.5 v 100 a v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 70 a v ih = v dd and v il = gnd i dd (all power-down modes) v dd = 4.5 v to 5.5 v 0.2 1 a v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 0.05 1 a v ih = v dd and v il = gnd power efficiency i out /i dd tbd % i load = 2 ma and v dd = 5 v 1 temperature ranges are as follows: b vers ion: C40c to +125c, typical at +25c. 2 linearity calculated using a reduced code range. 3 guaranteed by design and characterization, not production tested.
AD5641 prelim inary technical data r e v. pr c | pa g e 4 of 20 timing characteristics v dd = 2.7 v t o 5.5 v ; al l s p ec if ic a t io n s t min to t max , u n l e ss ot he r w i s e note d. s e e f i g u re 2 . table 3. p a r a m e t e r l i m i t 1 u n i t t e s t condition s / c o m m e n t s t 1 2 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 12 ns min sclk low time t 4 1 3 n s m i n sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 n s m i n sclk falling edge to sync rising edge t 8 3 3 n s m i n minimum sync high time t 9 1 3 n s m i n sync rising edge to next sclk fall ignore 1 a l l i n put si gn a ls a r e sp eci f i e d wi t h t r = t f = 1 n s / v (10% t o 90% of v dd ) a n d t i m e d from a volt a g e lev e l o f (v il + v ih )/2. 2 ma xi m u m s c lk fre q uen c y i s 30 mh z. t 4 t 3 t 2 t 5 t 7 t 6 d0 d1 d2 d14 d15 din sync sclk 04611-a - 002 t 9 t 1 t 8 d15 d14 f i g u re 2. ti ming d i ag r a m
prelim inary technical data AD5641 r e v. pr c | pa g e 5 of 20 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 4. p a r a m e t e r r a t i n g v dd to gnd ?0.3 v to +7.0 v digital input voltage to gnd C0.3 v to v dd + 0.3 v v ou t to gnd C0.3 v to v dd + 0.3 v operating tem p erature range industrial (b version) C40c to +125c storage temperature range C65c to +160c maximum junction temperature 150c sc70 package ja thermal impedance 332c/w jc thermal impedance 120c/w lead temperature, soldering vapor phase (60 s) 215c infrared (15 s) 220c e s d 2 . 0 k v s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd caution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
AD5641 prelim inary technical data r e v. pr c | pa g e 6 of 20 pin conf iguration and fu nction descriptions top view (n ot to scal e) v dd gnd sc lk din AD5641 v out sync 1 2 3 6 5 4 04611-a - 003 f i g u re 3. 6-l e ad sc 70 p i n conf ig ur at i o n ta ble 5. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1 sync level-triggered control input (active lo w). this is the frame sync hronizati o n sign al for the input data. when sync goes lo w, it ena b les the in put shift register, and d a ta is tr ansferred in on the falli ng ed ge s of the clocks that follow. t h e dac is updated following t h e 16 th cloc k cycle unles s sync is taken high before this edge, in whic h case the rising edge of sync acts as an interru pt and the write sequence is ign o red by the dac. 2 s c l k serial clock input. data is cl ocked into the input shift register on the falli ng edge of the serial cl ock input. data can be transferred at rates up to 30 mhz. 3 d i n serial data inpu t. this device has a 16-bit shift register. da ta is clocked into the register on the falling edge of the serial c l oc k inpu t. 4 v dd power supply input. the ad564 1 can be oper a ted from 2.7 v to 5.5 v. v dd should be decoupled to gnd. 5 gnd ground reference point for all circuitry on the AD5641. 6 v ou t analog output voltage from the dac. the o utp ut amplifier has rail-to-rai l oper a tion.
preliminary technical data AD5641 rev. prc | page 7 of 20 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl versus code plot can be seen in figure 4. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl versus code plot can be seen in figure 7. zero-code error zero-code error is a measure of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the AD5641, because the output of the dac cannot go below 0 v. zero-code error is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in mv. a plot of zero-code error versus temperature can be seen in figure 6. full-scale error full-scale error is a measure of the output error when full-scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in percent of full-scale range. a plot of full-scale error versus temperature can be seen in figure 6. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal, expressed as a percent of the full-scale range. tot a l un a dju s te d e r ror total unadjusted error (tue) is a measure of the output error taking all the various errors into account. a typical tue versus code plot can be seen in figure 5. zero-code error drift zero-code error drift is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 18. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.
AD5641 prelim inary technical data r e v. pr c | pa g e 8 of 20 typical perf orm ance cha r acte ristics code 04611-a - 004 ?1.5 ?1.0 ?0.5 0 1.0 0.5 1.5 2.0 2.5 0 2 k 4 k 6 k 8 k 10k 12k 14k 16k i n l e rro r ( l s b s ) f i g u re 4. t y pic a l in l plot 0 2 4 6 8 10 12 14 16 18 256 2k 4k 6k 8k 10k 12k 14k 16k tue (ls b s) code 04611-a - 005 f i gure 5. t o ta l u n a d jus t ed e r r o r f i gure 6. zero -s c a l e e rror and f u ll- s c a l e e r r o r v s . t e mpe r a t ur e ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 2 k 4 k 6 k 8 k 10k 12k 14k 16k dnl e rror (ls b s ) code 04611-a - 007 f i g u re 7. t y pic a l d n l pl ot f i gure 8. inl and d n l vs . sup p ly fi g u r e 9 . i dd his t og r a m @ v dd = 3 v/ 5 v
prelim inary technical data AD5641 r e v. pr c | pa g e 9 of 20 ?0 .6 ?0 .4 ?0 .2 0.0 0.2 0.4 0.6 0.8 ? 1 5 ?10 ? 5 0 5 1 0 15 i( m a ) ? v o (v ) 04611-a - 010 dac loaded with ff code v dd = 5v t a = 25 c dac loaded with 00 code f i gure 10. s o urc e and sink curr ent capabilit y f i gure 11. sup p l y current v s . t e mper at ur e f i g u re 12. f u ll- s c al e s e t t ling ti me f i gure 13. sup p l y current v s . code f i gure 14. sup p l y current v s . sup p ly v o ltag e f i g u re 15. h a lf -s c a l e s e t t ling ti me
AD5641 prelim inary technical data r e v. pr c | pa g e 10 o f 20 ch2 ch1 04611-a - 016 v dd = 5v t a = 25 c v dd v out = 70mv ch1 1v, ch2, time base = 20 s/div f i g u re 16. p o wer - o n r e s e t to 0 v c h 1 1v, ch 2 5 v, time base = 50 s/div ch2 ch1 04611-a - 017 v dd v out v dd = 5v t a = 25 c f i g u re 17. v dd vs . v ou t ( p owe r - d ow n ) f i g u re 18. d i g i t a l- t o -a na log g l i t ch i m puls e 04611-a - 019 ch1 v dd = 5v t a = 25 c midscale loaded ch1 5uv/div f i g u re 19. 1 / f no is e , 0. 1 h z to 1 0 h z b a ndwidt h ch1 5v, ch2 1v, time base = 5 s/div ch1 ch2 v out clk 04783-c-020 v dd = 5v t a = 25 c f i g u re 20. e x it ing p o wer - d o wn f i gur e 2 1 . ha rm onic di stor ti on o n d i gi ta ll y gene r a te d w a v e fo rm
prelim inary technical data AD5641 r e v. pr c | pa g e 11 o f 20 0 20 40 60 80 100 120 140 0 5 10 15 20 25 frequency (mhz) i dd (ua) 04611-a - 023 3/4 scale full scale 1/4 scale midscale zero scale f i g u re 22. i dd vs . sclk vs . c o de noise spectral density 0 20 40 160 60 80 100 120 140 200 180 1k 10k 100k frequency code 0x2040 zero scale midscale full scale 04611-a - 024 nv/ hz f i gure 23. no ise s p ec tr a l d e ns it y
AD5641 prelim inary technical data r e v. pr c | pa g e 12 o f 20 gene ral description d/a secti o n the AD5641 d a c is fa b r ic a t e d o n a cm os p r o c es s. th e a r c h i t ec t u r e co nsis ts o f a s t r i n g d a c f o l l o w ed b y a n o u t p u t b u f f er a m plif ier . f i gur e 24 is a blo c k d i a g ram o f t h e d a c arch i t e c t u re. v dd v out gnd resistor network ref (+) ref ( ? ) output amplifie r dac regis te r 04611-a - 025 f i gu r e 2 4 . d a c a r ch i t ectu r e b e ca us e t h e in pu t co di n g t o t h e d a c is st ra ig h t b i na r y , t h e i d e a l out p ut vol t ag e i s g i ve n b y u 16384 d v v dd out w h er e d is t h e de cima l e q ui va l e n t o f t h e b i na r y co de t h a t is lo aded t o the d a c r e g i s t er ; i t c a n ra n g e f r o m 0 t o 16,384. resistor string the r e sis t o r s t r i n g s e c t ion is sho w n in f i gur e 2 5 . i t is sim p l y a s t r i n g o f r e sis t o r s, eac h o f val u e r . th e co de lo aded t o t h e d a c r e g i s t er det e r m i n es a t w h ich n o de o n t h e st r i n g t h e v o l t a g e is t a p p e d o f f t o b e fe d in t o t h e o u t p u t am plif ier . th e v o l t a g e is t a pp e d of f by cl o s i n g one of t h e s w itc h e s c o n n e c t i ng t h e st r i ng t o t h e am plif ier . b e ca us e i t is a st r i n g o f r e sist o r s, i t is gua r an - t eed m o n o t o n i c. r r r r r to output amplifier 04611-a - 026 f i gur e 2 5 . resi st or str i ng sectio n outpu t am plifier t h e o u t p u t b u f f er a m p l if ier is ca p a b l e o f g e n e ra tin g rail-t o-rail vo lt age s on it s o u tput , g i v i ng a n output r a nge of 0 v to v dd . i t i s ca p a b l e o f dr ivin g a lo ad o f 2 k? in p a ral l e l wi t h 1000 pf t o gnd . th e s o urce an d sink c a p a b i li t i es o f t h e ou t p ut a m pl if ier ca n be s e en in f i gur e 10. th e s l ew ra t e is 0.5 v/s, wi t h a half- sc al e set t l i n g t i m e o f 8 s w i t h th e o u t p u t u n l o a d ed . serial interface the AD5641 has a 3-wir e s e r i al in t e r f ace ( sy n c , s c l k , a n d d i n) tha t is com p a t i b le wi th s p i, qs p i , a nd m i cr o w i r e in t e r f ace st andar d s as w e l l as most ds p s . s e e f i gur e 2 fo r a t i min g d i a g ram o f a ty p i ca l wr i t e s e q u e n ce. the wr i t e s e q u e n ce b e g i n s b y b r in g i n g t h e sy n c lin e lo w . d a ta f r o m t h e d i n li n e is clo c k e d i n to t h e 16- b i t shif t r e g i st er o n t h e fa l l in g e d ge o f s c lk. t h e s e r i a l clo c k f r e q uen c y ca n b e as hig h as 30 mh z, mak i n g the AD5641 co m p a t i b le wi th hig h sp ee d ds p s . o n t h e 1 6 th falli n g c l oc k ed g e , th e las t da ta b i t i s c l ock e d in and t h e p r og ra mme d f u n c t i o n is exe c u t e d ( a cha n ge in d a c r e g i s t er co n t en t s a nd/o r a cha n g e in t h e m o de o f o p era t io n). a t th i s s t a g e , th e sy n c l i n e m i gh t be k e p t l o w o r b r o u gh t h i gh . i n ei ther cas e , i t m u s t be b r o u g h t hig h f o r a minim u m o f 33 n s b e fo r e t h e n e xt wr i t e s e q u e n ce s o t h a t a fal l i n g e d g e o f sy n c ca n ini t i a t e t h e n e xt wr i t e s e q u en c e . b e ca us e t h e sy n c b u f f er dra w s m o r e c u r r en t w h e n v in = 1.8 v t h a n i t do es w h en v in = 0.8 v , sy n c s h o u ld be idle d l o w bet w een w r i t e s e q u e n ce s f o r ev e n l o w e r po w e r o p e r a t i o n o f th e p a r t , as me n t i o ne d ab ove. h o we ve r , i t m u st b e b r ou g h t h i g h ag ai n j u s t b e fore t h e ne x t w r i t e s e qu e n c e . inpu t shift register the in p u t shif t r e g i s t er is 16 b i ts wide (s ee f i gu r e 26). th e f i rs t tw o b i ts a r e con t r o l b i ts t h a t de ter m in e t h e p a r t s m o de o f op e r a t i o n ( n or m a l m o d e or a n y one of t h re e p o we r - d o w n m o de s). f o r a co m p lete de s c r i pt io n o f t h e va r i o u s m o des, s e e t h e p o w e r - d o w n m o des s e c t ion. th e n e xt 16 b i ts a r e t h e da t a b i ts, w h ich a r e t r a n sfer r e d t o t h e d a c r e g i st er o n t h e 16 th fallin g ed g e o f sc l k . data bits db15 (msb) db0 (lsb) pd1 pd0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 normal operation 1 k : to gnd 100 k : to gnd three-state power-down modes 0 0 1 1 0 1 0 1 04611-a - 027 f i gure 2 6 . input regi st er co ntents
prelim inary technical data AD5641 r e v. pr c | pa g e 13 o f 20 04611-a - 028 din db 1 5 db 16 d b 0 db0 invalid write sequence: sync high before 16 th falling edge valid write sequence, output updates on the 16 th falling edge sync sclk f i g u re 27. sy nc interr up t f a ci lit y sync interrupt i n a n o rm al w r i t e seq u en ce , th e sy n c lin e is k e p t lo w f o r a t le ast 16 fa l l in g e d ges o f sclk and t h e d a c is up d a te d on t h e 16 th fal l in g edge . h o w e v e r , if sy n c i s b r o u gh t hi gh bef o r e th e 16 th fa l l in g e d ge, t h is ac ts as an i n t e r r u p t t o t h e wr i t e s e q u e n ce. the s h if t r e g i s t e r is r e s e t a nd t h e wr i t e s e q u e n c e is s e en as in valid . n e i t h e r a n u p da te o f the d a c r e g i st er co n t en ts n o r a cha n g e i n t h e op era t i n g m o de o c c u rs (s e e f i gur e 27). power-on reset the AD5641 con t a i n s a p o w e r - o n r e s e t cir c ui t tha t con t r o ls the o u t p ut v o l t a g e d u r i n g p o w e r - u p . the d a c r e g i s t er is f i l l e d wi t h zer o s a nd t h e ou t p ut v o l t a g e is 0 v . i t r e ma in s t h er e un t i l a vali d wr i t e s e q u en ce is made t o t h e d a c. this is us ef u l in a p p l ic a - t i o n s in w h ich i t is im p o r t a n t to k n o w t h e st a t e o f t h e d a c s o u t p ut w h i l e i t i s in t h e p r o c es s o f p o w e r i n g u p . power-down modes the AD5641 ha v e f o ur s e p a ra t e m o des o f o p era t io n. th es e mo d e s are s o f t w a re - p ro g r am m a bl e by s e tt i n g t w o bit s ( d b 1 5 a nd d b 14) in t h e co n t r o l r e g i s t e r . t a b l e 6 sh o w s h o w t h e s t a t e o f t h e b i ts co r r es p o n d s t o t h e m o de o f o p era t ion o f t h e de vi ce . table 6. modes of operation for the ad564 1 d b 1 5 d b 1 4 o p e r a t i n g m o d e 0 0 n o r m a l ope rati o n p o w e r - d o w n m o d e 0 1 1 k? to gnd 1 0 100 k? to gnd 1 1 t h r e e - s t a t e w h en b o t h b i ts a r e s e t t o 0, t h e p a r t w o rks n o r m al l y wi t h i t s n o r m al p o w e r c o n s um p t io n o f 100 a maxim u m a t 5 v . h o w e v e r , fo r t h e t h r e e p o w e r - do wn m o des, t h e s u p p l y c u r r en t fal l s t o <100 na a t 3 v . n o t o n l y do es the s u p p l y c u r r en t fal l , b u t t h e output st age i s a l s o i n te r n a l ly s w itc h e d f r om t h e output of t h e am plif ier t o a r e sist o r n e tw ork o f k n o w n va lues. this has t h e ad van t a g e t h a t t h e o u t p ut i m p e dan c e o f t h e p a r t is kn own w h i l e t h e p a r t is in p o w e r - do w n m o de . ther e a r e t h r e e dif f er en t opt i ons : t h e output i s c o n n e c t e d i n te r n a l ly to g n d t h rou g h a 1 k? r e sis t o r o r a 100 k? r e sis t or , o r th e o u t p u t is lef t o p en- c i rc u i te d ( t h r e e - s t a te ) . f i g u re 2 8 show s t h e output st age. p o we r - d o wn ci rcu i t r y r esi st o r network v ou t r esi st o r s t ri ng d a c a m p l if ie r 04611-a - 029 f i gure 28. o u tput s t age d u r i ng p o wer-d o wn t h e bi a s ge ne r a tor , output a m pl i f i e r , re s i stor st r i ng , a n d ot he r as s o c i a t e d li n e ar cir c ui t r y a r e all s h u t do wn w h en t h e p o w e r - d o w n m o d e i s acti v a t e d . h o w e v e r , th e co n t e n t s o f th e d a c r e g i s t er a r e una f fe c t e d w h e n i n p o w e r - do w n . th e t i me t o exi t p o w e r - do wn is typ i cal l y 2.5 s f o r v dd = 5 v a nd 5 s f o r v dd = 3 v . s e e f i gur e 20 f o r a p l o t . microprocessor interfacing AD5641 to adsp-2101/adsp-2103 interface f i gur e 29 s h o w s a s e r i al in t e r f ac e betw een t h e AD5641 a nd t h e ads p -2101/ads p -2103. th e ads p -2101 /ads p - 2103 sh o u ld b e s e t up to op e r a t e i n sp o r t t r ans m it a l te r n a t e f r am i n g mo d e . the ads p -2101 /ads p - 2103 s p o r t is p r og ra mmed thr o ug h t h e sp or t c o n t rol re g i ste r and shou l d b e c o nf i g u r e d as fol l ows: in t e r n a l clo c k op era t ion, ac t i v e lo w f r a m in g, a nd 16- b i t w o r d len g t h . t r a n smi s sio n is in i t ia t e d b y wr i t in g a w o r d t o t h e tx r e g i s t er a f t e r t h e s p o r t has b e en ena b le d . a d sp - 2 10 1/ adsp-2103* AD5641* *additional pins omitted for clairty tfs dt sclk sync din sclk 04611-a - 030 f i gur e 2 9 . ad56 41 t o adsp -2 10 1/ adsp -2 10 3 int e r f a c e
AD5641 prelim inary technical data r e v. pr c | pa g e 14 o f 20 AD5641 to 68hc11/68l1 1 interface f i gur e 30 s h o w s a s e r i al in t e r f ac e betw een t h e AD5641 a nd t h e 68h c11/68l11 micr o c o n tr ol ler . sck o f th e 68 h c 11/68l11 dr i v es t h e s c l k o f t h e ad564 1, w h i l e t h e mo s i o u t p u t dr i v es t h e s e r i al da t a li n e o f t h e d a c. the sy n c sig n a l is der i ve d f r o m a p o r t line (pc7). t h e s e t u p co n d i t io n s f o r co r r ec t o p era t ion o f this in t e r f ace a r e as f o l l o w s: th e 68 h c 11/68l11 s h o u ld b e co nf igur ed s o tha t i t s cpo l b i t is a 0 a nd i t s cp h a b i t i s a 1. w h en da ta i s be in g tra n sm i t t e d t o t h e d a c , th e sy n c lin e is ta k e n lo w (pc7). w h en th e 68 h c 11/68 l 11 is co nf igur ed as a b o v e , da ta a p p e a r in g on the m o s i o u t p u t is valid o n t h e fal l in g edg e o f s c k. s e r i al da t a f r o m th e 68 h c 1 1 /68l11 is tra n smi t t e d in 8 - b i t b y t e s wi th onl y eig h t fal l in g c l o c k e d g e s occurri n g i n th e tra n sm i t c y c l e . da t a i s tra n smi t t e d ms b f i r s t . t o lo ad da ta t o th e AD5641, pc7 is lef t lo w a f t e r th e f i rs t eig h t b i ts a r e t r a n sfer r e d , a nd a s e cond s e r i al wr i t e o p era t io n is p e r f o r m e d to t h e d a c. pc7 is t a k e n hig h a t t h e end o f t h is pro c e d u r e. 68hc11/ 68l11 AD5641* *additional pins omitted for clairty pc7 sck mosi sync sclk din 04611-a - 031 f i gur e 3 0 . ad56 41 t o 6 8 h c 11 /68 l 11 int e r f a c e AD5641 to blackfin? adsp-b f53x interface f i gur e 31 s h o w s a s e r i al in t e r f ac e betw een t h e AD5641 a nd t h e b l ac kf in ads p -b f53x micr o p r o ces s o r . the ads p -b f53x p r o c es s o r fa mi ly in co r p o r a t es t w o d u al -cha nnel syn c hr o n o u s s e r i a l p o r t s, s p or t1 and s p or t0, fo r s e r i a l and m u l t i p r o cess o r co mm unic a t io ns. u s in g s p o r t0 t o co nnec t t o th e AD5641, t h e s e t u p fo r t h e in ter f ace is as fol l o w s: dt0 p ri dr iv es t h e s d i n p i n o f the ad56 41, while t s cl k0 dr i v es t h e s c lk o f the p a r t . the sy n c is dr i v en f r o m tfs0. adsp-bf53x AD5641 *additional pins omitted for clairty dt0pri tsclk0 tfs0 din sclk sync 04611-a - 032 f i gur e 3 1 . ad56 41 t o bl ac kfi n adsp -bf5 3x inte r f ac e AD5641 to 80c51/80l5 1 interface f i gur e 32 s h o w s a s e r i al in t e r f ac e betw een t h e AD5641 a nd t h e 80c51/80l51 micr o c o n tr ol ler . th e s e t u p f o r the in t e r f ace is as f o l l o w s: t x d o f th e 80c51 /80l 51 dr i v es sclk o f th e AD5641, w h i l e r x d dr i v es t h e s e r i al da t a li n e o f t h e p a r t . th e sy n c sig n a l is a g a i n d e r i ve d f r o m a b i t p r o g r a mma b l e p i n on t h e p o r t . i n t h is c a s e , p o r t line p3.3 is us e d . w h en d a t a is t o b e t r an smi t - t e d t o t h e ad56 41, p3.3 is tak e n lo w . the 80c51/80l 51 tra n smi t s da t a o n l y in 8 - b i t b y t e s; th er ef o r e , o n l y eig h t fal l i n g clo c k e d g e s o c c u r in t h e t r an s m i t c y cle . t o lo ad da ta t o th e d a c, p3.3 is lef t lo w a f t e r th e f i rs t eig h t b i ts a r e t r a n s m i t t e d , a n d a s e c o n d w r it e c y c l e i s i n it i a t e d t o t r a n s m it t h e s e con d b y te o f da ta . p3.3 is t a k e n hig h f o l l o w in g th e co m p letio n o f this c y c l e . th e 80c51/80l51 o u t p u t s the s e r i al da ta in a f o r m a t tha t has th e l s b f i rs t. the AD5641 r e q u ir es i t s da t a wi t h th e ms b as t h e f i rs t b i t r e cei v e d . th e 80 c51/80 l51 tra n smi t r o u t in e sh o u ld t a k e this in t o acc o un t. 80c51/80l51* AD5641* *additional pins omitted for clairty p3.3 txd rxd sync sclk din 04611-a - 033 f i g u re 32. a d 5 6 4 1 to 80c 51 /8 0l 51 int e r f ace AD5641 to microwire interface f i gur e 33 s h o w s a n in t e r f ace betw een t h e ad56 41 a nd an y mi cro w i r e c o m p a t i b le de vic e . s e r i a l da t a is shif te d o u t on th e fallin g ed ge o f th e se ri al c l o c k a n d i s c l ock e d i n t o th e AD5641 o n t h e r i sin g edg e o f th e s k . microwire* AD5641* *additional pins omitted for clairty cs sk so sync sclk din 04611-a - 034 f i gur e 3 3 . ad56 41 t o micr ow ire inter f a c e
prelim inary technical data AD5641 r e v. pr c | pa g e 15 o f 20 appli c ations choosing a reference as power supply fo r AD5641 the AD5641 com e s in a t i n y sc70 p a c k a g e wi th les s tha n a 100 a s u p p l y c u r r en t. b e ca us e o f this, th e c h oice o f r e f e r e n c e dep e n d s on t h e a p plic a t ion r e quir em e n ts. f o r sp ace-s a vi n g a p p l ic a t ion s , th e ad r425 is a v a i la b l e in an sc70 p a c k a g e and has exce l l en t dr i f t a t 3 p p m/c. i t a l s o p r o v ides v e r y go o d n o is e p e r f o r ma n c e a t 3.4 v p-p in t h e 0.1 h z t o 10 h z ra n g e . b e ca us e the s u p p l y c u rr en t r e q u ir ed b y the ad5 641 is extr em e l y lo w , i t is ideal f o r lo w s u p p l y a p p l ica t ion s . th e ad r293 v o l t a g e r e fer e n c e is r e c o mmende d in t h is cas e . this r e q u ir es 15 a o f q u ies c en t c u r r en t and can, t h erefo r e , dr i v e m u l t i p le d a cs in o n e syst em, if r e q u ir e d . ad 5641 3-wire serial interface sync sclk din 7v 5v v out = 0v to 5v ad r 4 2 5 04611-a - 035 f i g u re 34. a d r 4 2 5 as p o wer sup p l y t o a d 56 41 s o me r e co m m e n de d p r e c ision r e fer e n c es fo r us e as sup p lies to th e AD5641 a r e lis t ed in t a b l e 7. table 7. precision r e fere nces for use with AD5641 part no . initial accu racy (mv max) temperature drift (ppm/c max) 0.1 hz to 10 hz n o ise (v p-p typ) a d r 4 3 5 6 3 3 . 4 a d r 4 2 5 6 3 3 . 4 a d r 0 2 5 3 1 5 a d r 3 9 5 6 2 5 5 bipolar operation using the AD5641 the AD5641 has been desig n e d f o r sin g le-s u p p l y o p era t io n, b u t a b i p o la r o u t p ut ra n g e is a l s o p o ssi b le usin g t h e cir c ui t in f i g u re 3 5 . t h e c i rc u i t i n fi g u re 3 5 g i ve s an outp ut vo lt age r a nge o f 5 v . r a i l -t o- ra i l o p era t ion a t t h e am plif ier ou t p ut is ac hievab le using a n ad820 o r o p 295 as th e ou t p u t a m p l if ier . the o u t p u t v o l t a g e fo r a n y i n p u t co de c a n b e ca lc u l a t e d as fol l o w s: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = 1 1 2 1 16384 r 2 r v r r r d v v dd dd o wher e d r e p r es en ts t h e in p u t c o de in decimal (0 C 16384). w i t h v dd = 5 v , r1 = r2 = 10 k?: v 5 16384 10 ? ? ? ? ? ? ? = d v o this is an o u t p u t v o l t a g e ran g e o f 5 v wi th 0x 0000 co r r e- s p o n d i n g t o a C5 v o u t p u t , an d 0x3fff co r r es po n d in g t o a +5 v o u t p u t . r2 = 10k 04611-a - 036 ? +5v ?5 v ad 820/ op295 3-wire serial interface +5v AD5641 10 f 0. 1 f v dd v out r1 = 10k ? 5v f i gure 35. bipolar o p er at ion with the AD5641
AD5641 prelim inary technical data r e v. pr c | pa g e 16 o f 20 using AD5641 with an opto-isolated interface i n p r o c ess - con t r o l a p plica t io n s in i n d u st r i a l e n vir o nm e n ts, i t is of te n ne c e ss ar y to u s e an opto - i s o l a t e d i n te r f ac e to prote c t and is ola t e the co n t rol l in g cir c ui tr y f r o m a n y ha za r d o us co mm on- m o de v o l t a g es th a t mi gh t occu r i n t h e a r ea wh er e th e d a c i s f u n c t i o n in g. o p t o -is o la t o rs p r o v ide i s ola t io n i n excess o f 3 kv . b e ca us e the AD5641 us es a 3-wir e s e r i al log i c in t e r f ace , i t r e q u ir es o n ly t h r e e o p t o -is o l a t o rs t o p r o v ide t h e r e q u ir e d iso l a t io n (see f i gur e 36). t h e p o w e r s u p p l y t o th e p a r t also n e e d s t o b e iso l a t e d . t h is is do n e b y usin g a tr a n sf o r m e r . on th e d a c s i d e of t h e t r ans f or me r , a 5 v re g u l a tor pr ov i d e s t h e 5 v s u p p l y r e q u ir ed f o r th e AD5641 . v dd 0.1 f v dd v dd 10k ? 10k ? 10k ? +5v regula to r v out gnd 04611-a - 037 din sync sclk powe r 10 f v dd sync sclk da ta AD5641 f i gure 3 6 . ad56 41 wi th a n o p to -isol a t e d inter f ac e power supply bypass ing and gr ounding w h en acc u rac y is im p o r t an t i n a cir c ui t, i t is hel p f u l to ca r e f u l l y co n s ider t h e p o w e r s u p p ly a n d g r o u n d r e t u r n l a yo u t o n t h e bo a r d . th e p r in t e d cir c ui t bo a r d co n t a i nin g t h e AD5641 s h o u l d ha ve s e p a r a te ana l o g a n d dig i t a l s e c t io n s , e a ch ha vin g i t s o w n a r e a o f t h e b o a r d . i f t h e ad564 1 is in a syst em wher e o t h e r de vices r e q u ir e a n a g nd to d g n d co nn ecti o n , th e co nn ecti o n shou l d b e m a d e a t o n e p o i n t on ly . t h i s g r ou nd p o i n t s h ou l d b e as c l os e t o th e AD5641 as p o s s ible . the p o w e r s u p p l y t o th e ad564 1 s h o u ld be b y p a s s e d wi t h 10 f a n d 0 . 1 f ca p a ci t o rs. the ca p a c i t o rs sh ou ld be ph ysical ly as clos e as p o ssib le to t h e d e vi c e , wi t h t h e 0.1 f ca p a ci to r ide a l l y r i g h t u p a g a i n s t t h e de vi ce . th e 10 f c a p a ci t o rs a r e t h e ta n t al u m bead type . i t i s i m po r t a n t tha t th e 0 . 1 f c a pa c i t o r ha v e lo w ef fe c t i v e s e r i es r e sis t a n ce (esr) an d e f fe c t i v e s e r i es ind u c t an ce (es i ), s u c h as in comm on ceramic typ e s o f ca p a c i - t o rs. this 0.1 f ca p a ci t o r p r o v ides a lo w im p e da n c e p a th t o g r o u n d fo r hig h f r e q uen c ies c a us e d b y t r a n sie n t c u r r en ts d u e t o in t e r n a l log i c swi t chi n g. the p o w e r s u p p l y lin e i t s e lf sh ou ld ha v e as la rge a trace as pos s i b l e t o p r o v i d e a l o w i m peda n c e pa th a n d r e d u c e gli t c h e f fe c t s on t h e sup ply l i ne. c l o c k s and ot he r f a st s w i t ch ing d i g i t a l s i g n a l s shou l d b e sh i e l d e d f r om ot he r p a r t s of t h e b o ard by dig i t a l g r o u nd . a v o i d cr o s s o ver o f dig i t a l and ana l o g sig n a l s, if p o s s i b le . w h e n t r aces cr os s o n o p p o si t e sides of t h e bo a r d , en s u r e tha t they r u n a t r i gh t an g l e s to e a ch ot he r to re d u c e fe e d t h r o ug h ef fe c t s t h r o ug h t h e bo a r d . the be s t bo a r d la yo u t t e chni q u e is t h e micr os t r i p t e chniq u e w h er e t h e co m p on e n t side o f t h e b o a r d is de d i c a te d to t h e g r o u nd pl a n e on ly an d t h e signal traces a r e p l aced o n t h e s o lder side . h o w e v e r , this is n o t a l wa y s p o ssib le wi t h a 2 - l a yer b o a r d .
prelim inary technical data AD5641 r e v. pr c | pa g e 17 o f 20 outline dimensions 0. 22 0. 08 0. 46 0. 36 0. 26 8 4 0 0. 30 0. 15 1. 00 0. 90 0. 70 se a t i n g pl a n e 1. 10 m a x 4 2. 00 bs c pin 1 2. 10 bs c 0. 65 bs c 1. 25 bs c 1. 30 bs c 0. 10 m a x 0.10 coplanarity compliant to jedec standards mo-203ab f i gure 37. 6-l e ad p l astic su r f ace m o un t p a ck ag e [sc7 0] (k s-6) di me nsio ns sho w n i n mi ll im e t e r s ordering guide m o d e l t e m p e r a t u r e r a n g e d e s c r i p t i o n package descri ption package option AD5641bks C40c to +125c 4.0 lsb inl 6-lead plastic surface mount p a ckage (sc70) ks-6 AD5641aks C40c to +125c 8.0 lsb inl 6-lead plastic surface mount p a ckage (sc70) ks-6
AD5641 preliminary technical data rev. prc | page 18 of 20 notes
preliminary technical data AD5641 rev. prc | page 19 of 20 notes
AD5641 prelim inary technical data r e v. pr c | pa g e 20 o f 20 notes ? 2004 anal og dev i ces, inc. all rig h ts reserve d . tra d emar ks an d registered trad emar ks are th e pr op erty of t h eir respective owne rs. pr04611C0C6/04(p r c )

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